In high-powered ICs, such as, for example, high-powered application specific integrated circuits (ASICs), the di/dt current noise, also known as on-die power sag and brown out, can be extremely large. For example, much of the power consumed in a large CMOS IC is demanded in the first part of a clock cycle, which creates a power demand at a fundamental frequency associated with the rate of current change. This frequency is inherently different from the operating frequency of the IC due to clock distribution current demands, gate switching transients, and propagation delays through the gates, and may result in power noise in the IC which interferes with its performance as well as causing unwanted EMI.
FIG. 1 shows a typical waveform for a CMOS power noise event on die. When the clock transitions, much of the current is consumed in a small amount of time, which results in a net collapse of the on-die VDD level relative to the on-die ground. This is due to the effects of the current required to charge and discharge capacitance when switching the on-die clock distribution network, combined with the current required to switch on-die gates which have been activated by the clock.
Various techniques and designs have been used for reducing noise in ICs. One known technique utilizes on-package bypass capacitance, which is implemented using discrete capacitors. One disadvantage of this approach is that the effectiveness of the capacitors is severely limited by series inductance existing between the die (demand for charge) and the package capacitors (source of charge). As a result, the on-package capacitance provides only slightly better performance than using no capacitance at all. Furthermore, the frequency response of the network formed by the die attach, the package via inductances, the package trace and plane inductances, and the self inductance of the capacitors is not well matched to the frequency content of the incident on-die event. Consequently, the frequency response of this network is limited and is inadequate for handling the sharp peaks of the incident on-die event.
Another known technique utilizes on-package capacitance in the form of multiple power/ground plane layers on the package. This technique uses either solid or mesh power and ground planes, in either ceramic or organic packages. As with the technique that utilizes on-package bypass capacitance, the frequency response of the network formed by the die attach, the package via inductances, the package trace and plane inductances, and the self inductance of the capacitor formed by the planes is not well matched to the frequency content of the incident on-die event, and thus, is inadequate for handling the sharp peaks of the incident on-die event.
A technique implemented with printed circuit boards (PCBs) for reducing power noise utilizes on-board bypass capacitance, implemented either as discrete capacitors or as power/ground planes within the PCB or a combination of both. The frequency limitations discussed above are also inherent in this technique and are further exacerbated by additional inductance resulting from the chip-to-board package attach, the board via inductance, and the power-plane perforations.
Another known technique for reducing power noise and EMI in ICs utilizes intrinsic on-die capacitance formed by non-switching gates. The frequency response of the on-die capacitance formed by the non-switching gates is well matched to the incident power events by virtue of the fact that both are instantiated in the same material using the same connections. The primary problem associated with using intrinsic on-die capacitance is that the ratio of switching to non-switching gates is large in an efficient VLSI (very large scale integrated) circuit design. As utilization of the die area becomes more efficient, less capacitance will be available from non-switching gates because a larger percentage of the gates will be switching. Therefore, the number of non-switching gates available for capacitance is self-limiting.
Another known technique for reducing power noise and EMI on ICs utilizes extrinsic, or specifically instantiated, on-die capacitance. Although these capacitors provide a source of charge to supply on-die demands, which is well matched to the frequency content of the incident event, they do not provide a damping element. The resultant undamped power oscillations on package and die power structures can seriously degrade IC performance if they are co-incident with successive IC power events. The end result is super-positioning of resonant events with incident events, resulting in an overall higher noise amplitude at specific times.
On-package and on-die capacitance without loss elements must be carefully designed and implemented in order to avoid overlapping resonant frequencies, and the capacitances must be carefully chosen with regard to operating frequencies, package resonant frequencies, and board resonant frequencies. FIG. 2 shows a typical waveform for a CMOS power noise event on a die which has on-die capacitors without loss elements. Although the peak amplitude of the incident pulse is reduced when compared to that shown in FIG. 1, the under-damped power supply ringing causes sequential pulses to create a standing-wave condition with a specific frequency content. These undamped power oscillations can seriously degrade IC performance if they are co-incident with successive IC power events.
Accordingly, a need exists for a method and apparatus which is effective in reducing power noise and associated EMI in integrated circuit chips.